The present invention relates to a pipelined multiplier, and more particularly to a pipelined multiplier for signed multiplication or two's complement multiplication.
A multiplier is an essential part of any digital signal processing circuits. Since many numerical calculations can be ultimately reduced to multiplication, multiplication speed is a critical design parameter for many digital signal processing chips. Multiplier circuits arc thus often used as benchmark circuits for technology demonstration. Many different technologies have been used to fabricate multiplier circuits. For example, a fast 16.times.16 bit parallel array multiplier with 120-ns multiplication time was demonstrated using a 3 .mu.m E/D NMOS process technology, in the literature "A Fast 16 Bit NMOS Parallel Multiplier", Claude P. Lerouge et al., IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 3, pp. 338-342, June 1984. A 16-bit.times.16-bit multiplier for 2 two's complement binary numbers with 120-ns multiplication time was demonstrated using a standard n-E/D MOS process technology with 2.7 .mu.m design rule, in the literature "A High-Speed Multiplier Using a Redundant Binary Adder Tree", Yoshihisa Harata et al., IEEE Journal of Solid-State Circuits, Vol. SC-22 , No. 1, pp. 28-34, February 1987. A 3.8-ns 257-mW CMOS 16.times.16-bit multiplier was described in the literature "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic", Kazuo Yano et al., IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 388-395, April 1990. A 54.times.54-bit multiplier with 10-ns multiplication time was fabricated using double-metal 0.5-.mu.m CMOS technology, in the literature "A 10-ns 54.times.54-b Parallel Structured Full Array Multiplier with 0.5-.mu.m CMOS Technology", Junji Mori et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, pp. 600-605, April 1991. An 8-bit.times.8-bit parallel pipelined multiplier with 70-MHz multiplication rate was fabricated using 2.5-.mu.m CMOS technology, in the literature "A 70-MHz 8-bit.times.8-bit Parallel Pipelined Multiplier in 2.5-.mu.m CMOS", Mehdi Hatamian and Glenn L. Cash, IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 4, pp. 505-513, August 1986.
Recently, versatile microprocessor chips also have begun to contain multipliers, which is made possible by the rapid progress in integration technology. Therefore, the demand for improved multiplier performance is increasing.